`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   10:40:04 08/25/2014
// Design Name:   addr_mapping
// Module Name:   E:/Xilinx/Examples/ppc_no_cache/pcores/xps_mch_emc_v3_01_a/hdl/verilog/bcrm/testbench.v
// Project Name:  bcrm
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: addr_mapping
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module testbench;

	// Inputs
	reg Bus2IP_Clk_l;
	reg Bus2IP_Reset_l;
	reg [0:31] Bus2IP_Addr_l;
	reg [0:31] Bus2IP_Data_l;
	reg Bus2IP_RNW_l;
	reg [0:3] Bus2IP_BE_l;
	reg Bus2IP_Burst_l;
	reg [0:6] Bus2IP_BurstLength_l;
	reg Bus2IP_WrReq_l;
	reg Bus2IP_RdReq_l;
	reg [0:0] Bus2IP_CS_l;
	reg [0:0] Bus2IP_RdCE_l;
	reg [0:0] Bus2IP_WrCE_l;
	reg [0:31] IP2Bus_Data;
	reg IP2Bus_WrAck;
	reg IP2Bus_RdAck;
	reg IP2Bus_AddrAck;
	reg IP2Bus_Error;

	// Outputs
	wire [0:31] IP2Bus_Data_l;
	wire IP2Bus_WrAck_l;
	wire IP2Bus_RdAck_l;
	wire IP2Bus_AddrAck_l;
	wire IP2Bus_Error_l;
	wire Bus2IP_Clk;
	wire Bus2IP_Reset;
	wire [0:31] Bus2IP_Addr;
	wire [0:31] Bus2IP_Data;
	wire Bus2IP_RNW;
	wire [0:3] Bus2IP_BE;
	wire Bus2IP_Burst;
	wire [0:6] Bus2IP_BurstLength;
	wire Bus2IP_WrReq;
	wire Bus2IP_RdReq;
	wire [0:0] Bus2IP_CS;
	wire [0:0] Bus2IP_RdCE;
	wire [0:0] Bus2IP_WrCE;

	// Instantiate the Unit Under Test (UUT)
	addr_mapping uut (
		.Bus2IP_Clk_l(Bus2IP_Clk_l), 
		.Bus2IP_Reset_l(Bus2IP_Reset_l), 
		.IP2Bus_Data_l(IP2Bus_Data_l), 
		.IP2Bus_WrAck_l(IP2Bus_WrAck_l), 
		.IP2Bus_RdAck_l(IP2Bus_RdAck_l), 
		.IP2Bus_AddrAck_l(IP2Bus_AddrAck_l), 
		.IP2Bus_Error_l(IP2Bus_Error_l), 
		.Bus2IP_Addr_l(Bus2IP_Addr_l), 
		.Bus2IP_Data_l(Bus2IP_Data_l), 
		.Bus2IP_RNW_l(Bus2IP_RNW_l), 
		.Bus2IP_BE_l(Bus2IP_BE_l), 
		.Bus2IP_Burst_l(Bus2IP_Burst_l), 
		.Bus2IP_BurstLength_l(Bus2IP_BurstLength_l), 
		.Bus2IP_WrReq_l(Bus2IP_WrReq_l), 
		.Bus2IP_RdReq_l(Bus2IP_RdReq_l), 
		.Bus2IP_CS_l(Bus2IP_CS_l), 
		.Bus2IP_RdCE_l(Bus2IP_RdCE_l), 
		.Bus2IP_WrCE_l(Bus2IP_WrCE_l), 
		.Bus2IP_Clk(Bus2IP_Clk), 
		.Bus2IP_Reset(Bus2IP_Reset), 
		.IP2Bus_Data(IP2Bus_Data), 
		.IP2Bus_WrAck(IP2Bus_WrAck), 
		.IP2Bus_RdAck(IP2Bus_RdAck), 
		.IP2Bus_AddrAck(IP2Bus_AddrAck), 
		.IP2Bus_Error(IP2Bus_Error), 
		.Bus2IP_Addr(Bus2IP_Addr), 
		.Bus2IP_Data(Bus2IP_Data), 
		.Bus2IP_RNW(Bus2IP_RNW), 
		.Bus2IP_BE(Bus2IP_BE), 
		.Bus2IP_Burst(Bus2IP_Burst), 
		.Bus2IP_BurstLength(Bus2IP_BurstLength), 
		.Bus2IP_WrReq(Bus2IP_WrReq), 
		.Bus2IP_RdReq(Bus2IP_RdReq), 
		.Bus2IP_CS(Bus2IP_CS), 
		.Bus2IP_RdCE(Bus2IP_RdCE), 
		.Bus2IP_WrCE(Bus2IP_WrCE)
	);

	initial begin
		// Initialize Inputs
		Bus2IP_Clk_l = 0;
		Bus2IP_Reset_l = 0;
		Bus2IP_Addr_l = 0;
		Bus2IP_Data_l = 0;
		Bus2IP_RNW_l = 0;
		Bus2IP_BE_l = 0;
		Bus2IP_Burst_l = 0;
		Bus2IP_BurstLength_l = 0;
		Bus2IP_WrReq_l = 0;
		Bus2IP_RdReq_l = 0;
		Bus2IP_CS_l = 0;
		Bus2IP_RdCE_l = 0;
		Bus2IP_WrCE_l = 0;
		IP2Bus_Data = 0;
		IP2Bus_WrAck = 0;
		IP2Bus_RdAck = 0;
		IP2Bus_AddrAck = 0;
		IP2Bus_Error = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
	
		always
		#5 Bus2IP_Clk_l = !Bus2IP_Clk_l;
		
	initial begin
		#10 Bus2IP_Reset_l = 1;
		#20 Bus2IP_Reset_l = 0;
	end
	
	initial begin
		#30
		#5
		@(posedge Bus2IP_Clk_l)
			Bus2IP_Addr_l = 5555;
			Bus2IP_Data_l = 0;
			Bus2IP_RNW_l = 1;
			Bus2IP_BE_l = 4;
			Bus2IP_Burst_l = 0;
			Bus2IP_BurstLength_l = 0;
			Bus2IP_WrReq_l = 0;
			Bus2IP_RdReq_l = 0;
			Bus2IP_CS_l = 1;
			Bus2IP_RdCE_l = 1;
			Bus2IP_WrCE_l = 0;
			IP2Bus_Data = 0;
			IP2Bus_WrAck = 0;
			IP2Bus_RdAck = 0;
		@(posedge Bus2IP_Clk_l)
			Bus2IP_Addr_l = 5555;
			Bus2IP_Data_l = 0;
			Bus2IP_RNW_l = 1;
			Bus2IP_BE_l = 4;
			Bus2IP_Burst_l = 0;
			Bus2IP_BurstLength_l = 0;
			Bus2IP_WrReq_l = 0;
			Bus2IP_RdReq_l = 0;
			Bus2IP_CS_l = 1;
			Bus2IP_RdCE_l = 1;
			Bus2IP_WrCE_l = 0;
			IP2Bus_Data = 123;
			IP2Bus_WrAck = 0;
			IP2Bus_RdAck = 1;
		@(posedge Bus2IP_Clk_l)
		   Bus2IP_Addr_l = 5555;
			Bus2IP_Data_l = 0;
			Bus2IP_RNW_l = 1;
			Bus2IP_BE_l = 4;
			Bus2IP_Burst_l = 0;
			Bus2IP_BurstLength_l = 0;
			Bus2IP_WrReq_l = 0;
			Bus2IP_RdReq_l = 0;
			Bus2IP_CS_l = 1;
			Bus2IP_RdCE_l = 1;
			Bus2IP_WrCE_l = 0;
			IP2Bus_Data = 0;
			IP2Bus_WrAck = 0;
			IP2Bus_RdAck = 0;
		@(posedge Bus2IP_Clk_l)
			Bus2IP_Addr_l = 5555;
			Bus2IP_Data_l = 0;
			Bus2IP_RNW_l = 1;
			Bus2IP_BE_l = 4;
			Bus2IP_Burst_l = 0;
			Bus2IP_BurstLength_l = 0;
			Bus2IP_WrReq_l = 0;
			Bus2IP_RdReq_l = 0;
			Bus2IP_CS_l = 1;
			Bus2IP_RdCE_l = 1;
			Bus2IP_WrCE_l = 0;
			IP2Bus_Data = 0;
			IP2Bus_WrAck = 0;
			IP2Bus_RdAck = 0;
		@(posedge Bus2IP_Clk_l)
			Bus2IP_Addr_l = 5555;
			Bus2IP_Data_l = 0;
			Bus2IP_RNW_l = 1;
			Bus2IP_BE_l = 4;
			Bus2IP_Burst_l = 0;
			Bus2IP_BurstLength_l = 0;
			Bus2IP_WrReq_l = 0;
			Bus2IP_RdReq_l = 0;
			Bus2IP_CS_l = 1;
			Bus2IP_RdCE_l = 1;
			Bus2IP_WrCE_l = 0;
			IP2Bus_Data = 456;
			IP2Bus_WrAck = 0;
			IP2Bus_RdAck = 1;
		@(posedge Bus2IP_Clk_l)
			Bus2IP_Addr_l = 0;
			Bus2IP_Data_l = 0;
			Bus2IP_RNW_l = 0;
			Bus2IP_BE_l = 0;
			Bus2IP_Burst_l = 0;
			Bus2IP_BurstLength_l = 0;
			Bus2IP_WrReq_l = 0;
			Bus2IP_RdReq_l = 0;
			Bus2IP_CS_l = 0;
			Bus2IP_RdCE_l = 0;
			Bus2IP_WrCE_l = 0;
			IP2Bus_Data = 0;
			IP2Bus_WrAck = 0;
			IP2Bus_RdAck = 0;
			
	end
      
endmodule

